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 unsafeperform.io
CPU modeling in C?aSH (23 September 2018)
| | gergo.erdi.hu
Very high-level simulation of a C?aSH CPU (15 September 2018)
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| | [AI summary] The author explains how to test their software CHIP-8 CPU implementation by running the Mealy machine directly without C?ASH's simulation layer and integrating it with SDL for interactive debugging.
| | jborza.com
CHIP-8 in hardware - part 1 (ALU) | Juraj's Blog
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| | I got into FPGAs with the intent of building a retro-computer. A couple of popular hardware implementation targets are Gameboy, NES, RISC-V and CHIP-8. Last year Ive done my practice round with 6502 and RISC-V emulators, both in C. CHIP-8 is a really nice virtual machine implemented on a number of computers since the 1970s, initially designed to make game development easier. After building a CHIP-8 emulator a couple of days ago I thought I know a lot about the simple platform to actualy start implementin...
| | gergo.erdi.hu
CPU modeling in C?aSH (23 September 2018)
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| | davquar.it
MIPS CPU with a single clock cycle | Davide Quaranta
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| The MIPS architecture is of type RISC and originated in 1981 from a research project by Prof. Hennessy at Stanford. This architecture is characterized by instructions of the same length, and is geared toward simplifying pipeline implementation.