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 domipheus.com
Designing a CPU in VHDL, Part 7: Memory Operations, Running on FPGA - Domipheus Labs
| | davquar.it
MIPS CPU with a single clock cycle | Davide Quaranta
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| | The MIPS architecture is of type RISC and originated in 1981 from a research project by Prof. Hennessy at Stanford. This architecture is characterized by instructions of the same length, and is geared toward simplifying pipeline implementation.
| | jborza.com
Adventures in hardware, part 2 - even lower level | Juraj's Blog
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| | Ive went through the first part of From Nand to Tetris course where I learnt to build a simple 16-bit computer called Hack from the digital building blocks (NAND gates). The course used its specific HDL (hardware definition language), which is a gentle way to shield a beginner from the ugliness of a real language, but to implement anything on a real FPGA board one needs to use VHDL or Verilog.
| | blog.eowyn.net
EccCPU - Error Correcting Code Central Processing Unit
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| | Proof-of-concept CPU where the instructions are hamming codes
| | egghead.io
Adding Custom Syntax Highlighting to a Theme in VSCode | egghead.io
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| VSCode Themes are a quick way to update the color scheme and syntax highlighting of your code, but you might find your favorite theme isn't quite perfec...