Explore >> Select a destination

You are here

 davquar.it
MIPS CPU with a single clock cycle | Davide Quaranta
| | blog.eowyn.net
EccCPU - Error Correcting Code Central Processing Unit
4.3 parsecs away

Travel
| | Proof-of-concept CPU where the instructions are hamming codes
| | domipheus.com
Designing a CPU in VHDL, Part 7: Memory Operations, Running on FPGA - Domipheus Labs
3.7 parsecs away

Travel
| | This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing. Memory Operations We already have a small RAM which holds our instruction stream, but our TPU ISA defines memory read and write instructions, and we should get those instructions working. It's the last major functional implementation we need to complete. The fetch stage is simply a memory read with the PC...
| | craigjb.com
FPGA Game Boy Part 4: Loading immediate values and halting the CPU ยท Craig J. Bishop
4.3 parsecs away

Travel
| | [AI summary] This post discusses the implementation of load-immediate instructions and the halt instruction in the Game Boy CPU using SpinalHDL for FPGA simulation.
| | gpfault.net
Let's Learn x86-64 Assembly! Part 3 - Arithmetic and Logic
21.9 parsecs away

Travel
| [AI summary] The text provides an in-depth exploration of various x86-64 instruction set architectures, focusing on arithmetic operations (ADD, SUB, MUL, SMUL, DIV, SDIV), logical operations (AND, OR, XOR, NOT), and control flow instructions. It details the implementation of these instructions in the QBX virtual machine, emphasizing how they emulate real x86-64 instructions while managing the flags register and handling different operand sizes (8-bit and 16-bit). The text also discusses the nuances of flag handling, register operations, and macro-based code generation to streamline instruction implementation.