Outer Web | Explore

/explore

Click through on any links that interest you or select the planets on the right to continue exploring the Outer Web.

You are here		www.righto.com Why the Z-80's data pins are scrambled
\|	\|	domipheus.com Designing a CPU in VHDL, Part 7: Memory Operations, Running on FPGA - Domipheus Labs	3.8 parsecs away Travel
\|	\|	This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing. Memory Operations We already have a small RAM which holds our instruction stream, but our TPU ISA defines memory read and write instructions, and we should get those instructions working. It's the last major functional implementation we need to complete. The fetch stage is simply a memory read with the PC...	3.8 parsecs away Travel
\|	\|	davquar.it MIPS CPU with a single clock cycle \| Davide Quaranta	4.9 parsecs away Travel
\|	\|	The MIPS architecture is of type RISC and originated in 1981 from a research project by Prof. Hennessy at Stanford. This architecture is characterized by instructions of the same length, and is geared toward simplifying pipeline implementation.	4.9 parsecs away Travel
\|	\|	justanotherdot.com What Makes Up a CPU? Ryan James Spencer	4.8 parsecs away Travel
\|	\|	the blog of Ryan James Spencer	4.8 parsecs away Travel
\|	\|	exercism.org It's Nibbly November	24.7 parsecs away Travel
\|		This month we're exploring assembly languages: x86-64 Assembly, MIPS Assembly and WebAssembly	24.7 parsecs away Travel