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 jborza.com
Adventures in hardware, part 2 - even lower level | Juraj's Blog
| | domipheus.com
Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, register file, testing - Domipheus Labs
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| | This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing! ISE WebPACK Design Software I'm using the Xilinx ISE WebPack suite of tools for this project. It's available here for Windows and Linux, for free. Once installed and set up, you can run the project navigator and create a new project. I'll go through some basic steps here, just for clarity - however this s...
| | blog.dave.tf
Getting started with FPGA hacking ยท blog.dave.tf
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| | crepererum.net
crepererum - FPGAs for Software Engineers
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| | gpfault.net
Let's Learn x86-64 Assembly! Part 3 - Arithmetic and Logic
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| [AI summary] The text provides an in-depth exploration of various x86-64 instruction set architectures, focusing on arithmetic operations (ADD, SUB, MUL, SMUL, DIV, SDIV), logical operations (AND, OR, XOR, NOT), and control flow instructions. It details the implementation of these instructions in the QBX virtual machine, emphasizing how they emulate real x86-64 instructions while managing the flags register and handling different operand sizes (8-bit and 16-bit). The text also discusses the nuances of flag handling, register operations, and macro-based code generation to streamline instruction implementation.