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 domipheus.com
Designing a CPU in VHDL, Part 2: Xilinx ISE Suite, register file, testing - Domipheus Labs
| | jborza.com
Adventures in hardware, part 2 - even lower level | Juraj's Blog
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| | Ive went through the first part of From Nand to Tetris course where I learnt to build a simple 16-bit computer called Hack from the digital building blocks (NAND gates). The course used its specific HDL (hardware definition language), which is a gentle way to shield a beginner from the ugliness of a real language, but to implement anything on a real FPGA board one needs to use VHDL or Verilog.
| | danielmangum.com
A Single-Cycle 64-Bit RISC-V Register File ยท Daniel Mangum
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| | It's a simple question really: how can you read and write to the same register in a single-cycle processor? If you have spent most of your life working with software, it is tempting to think of all events as happening sequentially. However, that sequential model that we have become so familiar with as software engineers is really an abstraction that hardware offers to us to help our simple brains reason about logic.
| | sidecartridge.com
Bridging Decades: Interfacing the '80s to 2023 - SidecarTridge
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| | Technical journey creating the SidecarTridge Multi-device, bridging 1980s Atari ST with modern tech, how the cartridge interface was leveraged to enhance it
| | blog.wokwi.com
Learn UART Using Wokwi Logic Analyzer - Part 1
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| Look into the raw Tx/Rx signals using Wokwi and PulseView. No hardware required!