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 www.snell-pym.org.uk
Snell-Pym ยป Processor architecture
| | incoherency.co.uk
James Stanley - Adventures in CPU design
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| | [AI summary] The author details their journey learning CPU design through FPGAs, discrete logic chips, and the Nand2Tetris course, while exploring various DIY computer architectures and planning their next project.
| | domipheus.com
Designing a CPU in VHDL, Part 3: Instruction Set Architecture, Decoder, RAM - Domipheus Labs
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| | This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing! Instruction Set Architecture The Instruction Set Architecture (ISA) of a CPU defines the set of operations that can be performed, and on what data types. It explains timing, restrictions, and sometimes any hazards or hardware bugs that can present during normal operation. The operations are defined along ...
| | www.righto.com
The 8086 processor's microcode pipeline from die analysis
3.0 parsecs away

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| | Intel introduced the 8086 microprocessor in 1978, and its influence still remains through the popular x86 architecture. The 8086 was a fai...
| | embecosm.com
A dive into RI5CY core internals - Embecosm
24.9 parsecs away

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| [AI summary] This article dives into the internals of the RI5CY core, a 4-stage in-order pipelined RISC-V core. It discusses the decoder and register file, essential for customizing the core, particularly for adding new instructions and integrating cryptographic extensions like XCrypto. The article also compares RISC-V's compressed instructions with ARM's Thumb mode, highlighting differences in code density and implementation.