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 domipheus.com
Designing a CPU in VHDL, Part 3: Instruction Set Architecture, Decoder, RAM - Domipheus Labs
| | incoherency.co.uk
James Stanley - Adventures in CPU design
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| | [AI summary] The author explores their journey into CPU design, discussing FPGA projects, DIY CPUs like Ben Eater's breadboard CPU and Magic-1, and reflections on learning Verilog and the Nand2Tetris course to build a simple CPU capable of running an OS.
| | www.snell-pym.org.uk
Snell-Pym » Processor architecture
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| | [AI summary] The article discusses various exotic processor architectures, focusing on zero-operand stack machines, multiple stacks, result registers, virtual stacks, and transport-triggered architectures, highlighting their potential to simplify control logic and improve performance.
| | craigjb.com
FPGA Game Boy Part 4: Loading immediate values and halting the CPU · Craig J. Bishop
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| | [AI summary] This post discusses the implementation of load-immediate instructions and the halt instruction in the Game Boy CPU using SpinalHDL for FPGA simulation.
| | danilafe.com
Learning Emulation, Part 2.5 - Implementation
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