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gafferongames.com
| | erikmcclure.com
3.3 parsecs away

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| | Today, there was an announcement about a new RISC-V chip, which has got a lot of people excited. I wish I could also be excited, but to me, this is just a reminder that RISC architectures are fundamentally unscalable, and inevitably stop being RISC as soon as they need to be fast. People still call ARM a "RISC" architecture despite ARMv8.3-A adding a FJCVTZS instruction, which is "Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero". Reduced instruction set, my ass.
| | huonw.github.io
2.9 parsecs away

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| | An overview of my work on improving SIMD in Rust.
| | www.yosefk.com
1.1 parsecs away

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| | [AI summary] A technical article explaining how to achieve consistent floating-point computation results across different build modes and platforms by configuring compiler flags and FPU control registers to avoid platform-specific intermediate precision issues.
| | limpet.net
13.8 parsecs away

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| [AI summary] This article explains Rust's memory safety guarantees by reframing the compiler's borrowing and lifetime checks as a system of unique versus shared access to data.