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 unsafeperform.io
CPU modeling in C?aSH (23 September 2018)
| | jborza.com
CHIP-8 in hardware - part 1 (ALU) | Juraj's Blog
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| | I got into FPGAs with the intent of building a retro-computer. A couple of popular hardware implementation targets are Gameboy, NES, RISC-V and CHIP-8. Last year Ive done my practice round with 6502 and RISC-V emulators, both in C. CHIP-8 is a really nice virtual machine implemented on a number of computers since the 1970s, initially designed to make game development easier. After building a CHIP-8 emulator a couple of days ago I thought I know a lot about the simple platform to actualy start implementin...
| | danilafe.com
Learning Emulation, Part 2.5 - Implementation
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| | This is the third post in a series I'm writing about Chip-8 emulation. If you want to see the first one, head here.
| | riv.dev
Emulating a Computer: The CHIP-8 Interpreter - River Gillis [riv.dev]
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| | How to write a CHIP-8 emulator.
| | gpfault.net
Let's Learn x86-64 Assembly! Part 3 - Arithmetic and Logic
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| [AI summary] The text provides an in-depth exploration of various x86-64 instruction set architectures, focusing on arithmetic operations (ADD, SUB, MUL, SMUL, DIV, SDIV), logical operations (AND, OR, XOR, NOT), and control flow instructions. It details the implementation of these instructions in the QBX virtual machine, emphasizing how they emulate real x86-64 instructions while managing the flags register and handling different operand sizes (8-bit and 16-bit). The text also discusses the nuances of flag handling, register operations, and macro-based code generation to streamline instruction implementation.