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www.skrasser.com | ||
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blog.eowyn.net
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| | | | | The goal for this project was to develop a GPU-like core in VHDL for the Upduino v2 and v3. This would include a 60Hz 320x200 or 640x480 resolution output with read/write frame and color buffers, using PWM to increase the color depth. The color buffer would use color cells similar to those of the Commodore 64. However, due to limitations inherent in the Upduino, the full design was not realized. A simpler design with a text buffer was built instead. | |
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michaelscodingspot.com
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| | | | | Michael Shpilt's Blog on .NET software development, C#, performance, debugging, and programming productivity | |
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jborza.com
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| | | | | In the last part I ended up with a partially working CPU with most of the single-clock instructions implemented. So far, all of the testing was done in simulator only, and it's about time to to get a visual output, so I implemented the display sprite operation next. Other articles in the series: CHIP-8 in FPGA #1 (ALU) CHIP-8 in FPGA #2 (CPU) Display instruction: DXYN The DXYN opcode is described in the original manual as: | |
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peanball.net
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