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PB/80 computer concept - Retro Computer Blog
| | domipheus.com
Designing a CPU in VHDL, Part 3: Instruction Set Architecture, Decoder, RAM - Domipheus Labs
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| | This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing! Instruction Set Architecture The Instruction Set Architecture (ISA) of a CPU defines the set of operations that can be performed, and on what data types. It explains timing, restrictions, and sometimes any hazards or hardware bugs that can present during normal operation. The operations are defined along ...
| | austinmorlan.com
Building an FPGA Computer: SAP-1 - Austin Morlan
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| | Ive been getting into FPGAs lately. Last year I built an FPGA version of Ben Eaters breadboard computer, but Ive been wanting to do a more advanced project to help me gain experience with Verilog and FPGAs in general. For his breadboard computer, Ben Eater followed the design laid out in a book called Digital Computer Electronics by Malvino and Brown. The book builds what it calls the Simple-as-Possible (SAP) Computer.
| | jborza.com
CHIP-8 in hardware - part 2 (CPU) | Juraj's Blog
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| | Continuing with the implementation of CHIP-8 in Verilog, I wanted to continue with the CPU module and get it to actually execute some instructions, so we'll build an instruction decoder, CPU states and a register file. As described in the previous part , we would like to: fetch instruction (2 bytes) from the memory into an 16-bit opcode register decode the instruction execute the instruction Other articles in the series:
| | multigesture.net
How to write an emulator (CHIP-8 interpreter)
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| A multitouch and HCI research blog