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cpu.land | ||
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krinkinmu.github.io
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| | | | | I'm continuing my exploration of the AArch64 architecture and this time I will touch on the AArch64 priviledge levels. Note that AArch64 priviledge model is not exactly the same as the previous iterations of ARM. While there are plenty of similarities, and there is a level of backward compatibility, at the same time, there are some differences as well. So do not assume that things covered here will work the same way for all ARMs. Finally, I assume that you're familiar with general GNU Assembler synatax or willing to figure things out as you go. Familiarity with ARM assmebly language will help, though I try to explain all the things I use. As always the code is available on GitHub. | |
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lupyuen.org
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| | | | | We're porting Apache NuttX RTOS to Pine64's Star64 JH7110 RISC-V SBC... And we see interesting issues with RISC-V Privilege Levels and 16550 UART Registers | |
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blog.codingconfessions.com
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| | | | | An explanation of how Linux handles system calls on x86-64 and why they show up as expensive operations in performance profiles | |
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mouha.be
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| | | [AI summary] A cryptography researcher coordinates the public disclosure of a SHA-3 buffer overflow vulnerability found in the official XKCP implementation and related projects, detailing how the flaw allows for memory exhaustion and potential code execution. | ||
