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 lupyuen.org
Star64 JH7110 + NuttX RTOS: RISC-V Privilege Levels and UART Registers
| | blog.lenot.re
Symmetric MultiProcessing, Hyper-Threading and scheduling on Maestro
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| | A dive into the PIC, PIT, ACPI, APIC, HPET, SMP, TLB and other confusing acronyms!
| | jborza.com
Booting RISC-V on QEMU | Juraj's Blog
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| | For reference, I wanted to check how qemu boots RISC-V Linux. Loosely following a guide , I describe how to build and boot a Linux environment targeting the 32-bit RISC-V architecture. There are three things we will need: QEMU the emulator Linux kernel root filesystem with some binaries I'm reusing a custom riscv-gnu-toolchain I've built previously, targeting the RV32IMA architecure. For targeting the 64-bit machine, it's easier to riscv64-linux-gnu- cross-compiler toolchain with the gcc-riscv64-linux-gn...
| | book.hacktricks.xyz
Introduction to ARM64v8 - HackTricks
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| | disconnect3d.pl
When NULL isn't null: mapping memory at 0x0 on Linux
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| When we think of a null pointer, NULL in C or nullptr in C++, we typically assume it is "invalid" or "not pointing to a valid memory location". But what if I tell you that a null pointer can actual...