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 danielmangum.com
RISC-V Bytes: Privilege Levels · Daniel Mangum
| | kuruczgy.com
Porting Lean to the ESP32-C3 RISC-V microcontroller
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| | domipheus.com
Designing a RISC-V CPU in VHDL, Part 18: Control and Status Register Unit - Domipheus Labs
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| | This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing. You may remember after the switch from my own TPU ISA to RISC-V was made, I stated that interrupts were disabled. This was due to requirements for RISC-V style interrupt mechanisms not being compatible with what I'd done on TPU. In order to get Interrupts back into RPU, we need to go and implement the correct Control and Status Registers(CSRs) required for management of interrupts - enable bits, interrupt vectors, interrupt causes - they are all communicated via CSRs.
| | www.scottsmitelli.com
The Hidden Worlds of the Klein Tools TI250 Thermal Imager § Scott Smitelli
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| | A deep dive into hidden data encoded in the BMP files saved by the Klein Tools TI250 thermal imager.
| | www.github.com
Stargazers · Krayorn/blog · GitHub
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| my blog, with astro. Contribute to Krayorn/blog development by creating an account on GitHub.