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gamozolabs.github.io | ||
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paul.bone.id.au
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| | | | | CPU-bound performance often involves CPU caches. So lets dive in to CPU caches, some basics of how they're implemented, how they keep a consistent view... | |
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prog.world
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| | | | | [AI summary] The article discusses the use of Intel Processor Trace (PT) technology to capture code traces from the System Management Mode (SMM) in a computer's BIOS. The authors detail the process of creating a backdoor to access SMM, modifying the SMI dispatcher to redirect execution to a custom shellcode, and using tools like WinIPT and ptxed to analyze the trace data. They also mention challenges such as synchronization issues and the need for cross-platform compatibility, and conclude that this method provides an efficient way to investigate SMM code for vulnerabilities. | |
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membarrier.wordpress.com
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| | | | | In the previous post we saw how the memory management unit (MMU) uses page tables to translate virtual addresses into physical ones. We will now consider the various features that such a translation enables in an operating system. In the discussion below, it is important to remember that the granularity of translation is a single... | |
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bijanebrahimi.github.io
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