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danielmangum.com | ||
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jborza.com
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| | | | | A friend told me about a cool new open-source instruction set architecture called RISC-V (pronounced risk-five). As I wanted to learn more about the architecture, I decided writing an RISC-V emulator (emuriscv) would make sense. One of my goals include running a Linux on it, much inspired by Fabrice Bellard's awesome JSLinux project . I initially started using the same 32-bit RISC-V Linux image as per Bellard's technical notes , but I needed to add some of my own code for debugging purposes. | |
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www.righto.com
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| | | | | Interrupts have been an important part of computers since the mid-1950s, 1 providing a mechanism to interrupt a program's execution. Inte... | |
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domipheus.com
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| | | | | This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing. You may remember after the switch from my own TPU ISA to RISC-V was made, I stated that interrupts were disabled. This was due to requirements for RISC-V style interrupt mechanisms not being compatible with what I'd done on TPU. In order to get Interrupts back into RPU, we need to go and implement the correct Control and Status Registers(CSRs) required for management of interrupts - enable bits, interrupt vectors, interrupt causes - they are all communicated via CSRs. | |
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roadrunnertwice.dreamwidth.org
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