Explore >> Select a destination

You are here

 johnwickerson.wordpress.com
Fuzzing High-Level Synthesis Tools - Wickopedia
| | zipcpu.com
Clocks for Software Engineers
3.6 parsecs away

Travel
| | If you have a software background and you want to pick up digital design,then one of the first things you need to learn about early on is the conceptof the c...
| | incoherency.co.uk
James Stanley - Adventures in CPU design
7.2 parsecs away

Travel
| | [AI summary] The author explores their journey into CPU design, discussing FPGA projects, DIY CPUs like Ben Eater's breadboard CPU and Magic-1, and reflections on learning Verilog and the Nand2Tetris course to build a simple CPU capable of running an OS.
| | blog.dave.tf
Getting started with FPGA hacking ยท blog.dave.tf
7.0 parsecs away

Travel
| |
| | domipheus.com
Designing a RISC-V CPU in VHDL, Part 16: Arty S7 RPU SoC, Block Rams, 720p HDMI - Domipheus Labs
15.9 parsecs away

Travel
| This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing. It's finally time - the big deploy onto Digilent's Arty S7 board. In my previous part, I went over at a high level the changes made to my TPU cpu core in order to make it consume RISC-V. The CPU itself is still very simple, and I removed some of the more interesting features from TPU such as interrupts. I...