Explore >> Select a destination
|
You are here 
|
craigjb.com | ||
| | | | |
embecosm.com
|
|
| | | | | ||
| | | | |
jborza.com
|
|
| | | | | Continuing with the implementation of CHIP-8 in Verilog, I wanted to continue with the CPU module and get it to actually execute some instructions, so we'll build an instruction decoder, CPU states and a register file. As described in the previous part , we would like to: fetch instruction (2 bytes) from the memory into an 16-bit opcode register decode the instruction execute the instruction Other articles in the series: | |
| | | | |
domipheus.com
|
|
| | | | | This is part of a series of posts detailing the steps and learning undertaken to design and implement a CPU in VHDL. Previous parts are available here, and I'd recommend they are read before continuing. _This is a disclaimer that the VHDL here is probably not the best you will see, but it gets the job done - in the simulator, at least. If you spot any serious errors, or woeful performance gotchas I've fallen for - please let me know at @domipheus. The aim of these posts is to get a very simple 16-bit CPU up and running, and then get stuck into some optimization opportunities later. | |
| | | | |
blog.cleancoder.com
|
|
| | | |||
